View CS5124_269625.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Back
CS5124, CS5126 High Performance, Integrated Current Mode PWM Controllers
The CS5124/6 is a fixed frequency current mode controller designed specifically for DC-DC converters found in the telecommunications industry. The CS5124/6 integrates many commonly required current mode power supply features and allows the power supply designer to realize substantial cost and board space savings. The product matrix is as follows: CS5124: 400 kHz w/VBIAS Pin, 195 mV first current sense threshold. CS5126: 200 kHz w/SYNC Pin, 335 mV first current sense threshold. The CS5124/6 integrates the following features: Internal Oscillator, Slope Compensation, Sleep On/Off, Undervoltage Lock Out, Thermal Shutdown, Soft Start Timer, Low Voltage Current Sense for Resistive Sensing, Second Current Threshold for Pulse by Pulse Over Current Protection, a Direct Optocoupler Interface and Leading Edge Current Blanking. The CS5124/6 has supply range of 7.7 V to 20 V and is available in 8 pin SO narrow package. Features * Line UVLO Monitoring * Low Current Sense Voltage for Resistive Current Sensing * External Synchronization to Higher or Lower Frequency Oscillator (CS5126 Only) * Bias for Start Up Circuitry (CS5124 Only) * Thermal Shutdown * Sleep On/Off Pin * Soft Start Timer * Leading Edge Blanking * Direct Optocoupler Interface * 90 ns Propagation Delay * 35 ns Driver Rise and Fall Times * Sleep Mode
http://onsemi.com
8 1 SO-8 D SUFFIX CASE 751
PIN CONNECTIONS AND MARKING DIAGRAM
1 CS5124 8 5124 ALYW
VCC BIAS UVLO SS
GND GATE ISENSE VFB
VCC UVLO SYNC SS
1
CS5126 8 5126 ALYW
GND GATE ISENSE VFB
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS5124XD8 CS5124XDR8 CS5126XD8 CS5126XDR8 Package SO-8 SO-8 SO-8 SO-8 Shipping 95 Units/Rail 2500 Tape & Reel 95 Units/Rail 2500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
April, 2001 - Rev. 4
Publication Order Number: CS5124/D
CS5124, CS5126
36-75VIN L1 10 H R2 200 k C2 1.5 F 100 V R5 17.4 k R1 510 k CTX15-14514 T1 Q1 ZVN3310A D4 R4 10 BAS16LT1 Q2 IRFR220 C4 0.47 F 25 V VCC BIAS ENABLE UVLO CS5124 C9 1000 pF SS C7 0.1 F VFB C8 1000 pF GND GATE U2 IS 0.01 F D1 5VOUT MBRD360CT
R3 47
C1 0.1 F 100 V
C3 0.022 F
R6 1.0 k
R7 30.1 k
R8 0.39 C6
C5 47 F 10 V
TPS5908
R9 10 k
48VRTN ISOLATED RTN
Figure 1. Application Diagram
MAXIMUM RATINGS*
Rating Operating Junction Temperature, TJ Storage Temperature Range, TS ESD Susceptibility (Human Body Model) Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value -40 to 135 -40 to 150 2.0 230 peak Unit C C kV C
MAXIMUM RATINGS
PIN NAME VCC Power Input Clock Synchronization Input VCC Clamp Output UVLO Shutdown Input Soft Start Capacitor Input Voltage Feedback Input Current Sense Input Ground Gate Drive Output PIN SYMBOL VCC SYNC (CS5126) VBIAS (CS5124) UVLO SS VFB ISENSE GROUND GATE VMAX 20 V 20 V 20 V 6.0 V 6.0 V 6.0 V 6.0 V 0V 20 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V 0V -0.3 V ISOURCE 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 3.0 mA 1.0 mA 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC ISINK 1.5 A Peak 200 mA DC 1.0 mA 1.0 mA 1.0 mA 2.0 mA 20 mA 1.0 mA 1.0 mA 1.5 A peak 200 mA DC
http://onsemi.com
2
CS5124, CS5126
ELECTRICAL CHARACTERISTICS (-40C TJ 125C; -40C TA 105C, 7.60 V VCC 20 V, UVLO = 3.0 V, ISENSE = 0 V, CV(CC) = 0.33 F, CGATE = 1.0 nF (ESR = 10 ); CSS = 470 pF; CV(FB) = 100 pF, unless otherwise specified.)
Characteristic General ICC Operating - VGATE not switching ICC at VCC Low ICC Sleep Low VCC Lockout VCC Turn-on Threshold Voltage VCC Turn-off Threshold Voltage VCC Hysteresis UVLO Sleep Threshold Voltage Sleep Threshold Voltage Sleep Hysteresis UVLO Turn-off Threshold Voltage UVLO Turn-on Threshold Voltage UVLO Hysteresis UVLO Hysteresis UVLO Input Bias Current UVLO Clamp VCC Clamp and BIAS Pin VCC Clamp Voltage BIAS Minimum Voltage BIAS Clamp 200 kHz Oscillator Operating Frequency Max Duty Cycle Clamp Slope Compensation (Normal operation) Slope Compensation (Synchronized operation) SYNC Input Threshold Voltage SYNC Input Impedance 400 kHz Oscillator Operating Frequency Max Duty Cycle Clamp Slope Compensation Note 2 - Measured with SYNC = 1.0 V & 10 V CS5124 Only - - - 360 80.0 15 400 82.5 21 440 85.0 26 kHz % mV/s Note 2 Note 2 Turn-on - Turn-off (-40C TJ 100C) Note 2 Turn-on - Turn-off (100C TJ 125C) Note 2 - With UVLO sinking 1.0 mA UVLO decreasing UVLO increasing - 1.5 - 35 2.3 2.50 170 50 -1.0 5.0 1.8 1.88 85 2.45 2.63 185 185 - 7.5 2.3 2.45 150 2.6 2.76 200 400 1.0 12 V V mV V V mV mV A V - - - 7.2 6.8 350 7.7 7.3 425 8.3 7.8 500 V V mV VCC = 6.0 V VUVL = 1.0 V - - - - 10 500 210 13 750 275 mA A A Test Conditions Min Typ Max Unit
CS5124 Only. Connect an NFET as follows: BIAS = G, VCC = S, VIN = D. 36 V VIN 60 V, 200 nF CSS 500 nF, R = 500 k Measure Voltage on BIAS with: 10 V VCC 20 V & 50 A IBIAS 1.0 mA With BIAS pin sinking 1.0 mA CS5126 Only - - - 175 78 12 200 82.5 18 225 85 23 kHz % mV/s 7.275 1.6 12 7.9 2.8 15 8.625 4.0 20 V V V
7.0 1.0 50
12 2.0 120
16 3.0 230
mV/s V k
2. Not tested in production. Specification is guaranteed by design.
http://onsemi.com
3
CS5124, CS5126
ELECTRICAL CHARACTERISTICS (continued) (-40C TJ 125C; -40C TA 105C, 7.60 V VCC 20 V, UVLO = 3.0 V,
ISENSE = 0 V, CV(CC) = 0.33 F, CGATE = 1.0 nF (ESR = 10 ); CSS = 470 pF; CV(FB) = 100 pF, unless otherwise specified.) Characteristic Soft Start Soft Start Charge Current Soft Start Discharge Current VSS Voltage when VFB Begins to Rise Peak Soft Start Charge Voltage Valley Soft Start Discharge Voltage Current Sense First Current Sense Threshold Second Current Sense Threshold ISENSE to GATE Prop. Delay Leading Edge Blanking Time Internal Offset Current Sense First Current Sense Threshold Second Current Sense Threshold ISENSE to GATE Prop. Delay Leading Edge Blanking Time Internal Offset Voltage Feedback VFB Pull-up Res. VFB Clamp Voltage VFB Clamp Voltage VFB Fault Voltage Threshold Output Gate Drive Maximum Sleep Pull-down Voltage GATE High (AC) GATE Low (AC) GATE High Clamp Voltage Rise Time Fall TIme Thermal Shutdown Thermal Shutdown Temperature Thermal Enable Temperature Thermal Hysteresis Note 3 GATE low Note 3 GATE switching Note 3 135 100 15 150 125 25 165 150 35 C C C VCC = 6.0 V, IOUT = 1.0 mA Series resistance < 1.0 , Note 3 Series resistance < 1.0 , Note 3 VCC = 20 V Measure GATE rise time, 1.0 V < GATE < 9.0 V VCC = 12 V Measure GATE fall time, 9.0 V > GATE > 1.0 V VCC = 12 V - VCC - 1.0 - 11.0 - - 1.2 VCC - 0.5 0.0 13.5 45 25 2.0 - 0.5 16.0 65 55 V V V V ns ns CS5124 Only CS5126 Only - - 2.9 2.63 2.40 460 4.3 2.90 2.65 490 8.1 3.15 290 520 k V V mV CS5124 Only At max duty cycle - 0 to 700 mV pulse into ISENSE (after blanking time) 0 to 400 mV pulse into ISENSE Note 3 CS5126 Only At max duty cycle - 0 to 800 mV pulse into ISENSE (after blanking time) 0 to 550 mV pulse into ISENSE Note 3 300 485 60 110 - 335 525 90 175 125 360 575 130 210 - mV mV ns ns mV 170 250 60 90 - 195 275 90 130 60 215 315 130 180 - mV mV ns ns mV VFB = 300 mV - - - - 7.0 0.5 1.40 4.7 200 10 10.0 1.62 4.9 275 13 - 1.80 - 400 A mA V V mV Test Conditions Min Typ Max Unit
3. Not tested in production. Specification is guaranteed by design.
http://onsemi.com
4
CS5124, CS5126
PACKAGE PIN DESCRIPTION
PACKAGE PIN # 8 Lead SO Narrow CS5124 1 2 CS5126 1 - PIN SYMBOL VCC BIAS VCC Power Input Pin. VCC Clamp Output Pin. This pin will control the gate of an N-channel MOSFET that in turn regulates Vcc. This pin is internally clamped at 15 V when the IC is in sleep mode. Clock Synchronization Pin. A positive edge will terminate the current PWM cycle. Ground this pin when it is not used. Sleep and under voltage lockout pin. A voltage greater than 1.8 V causes the chip to "wake up" however the GATE remains low. A voltage greater than 2.6 V on this pin allows the output to switch. Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is charged with 10 A and discharged with 10 mA. The Soft Start capacitor controls both Soft Start time and hiccup mode frequency. Voltage Feedback Pin. The collector of an optocoupler is typically tied to this pin. This pin is pulled up internally by a 4.3 k resistor to 5.0 V and is clamped internally at 2.9 V (2.65 V). If VFB is pulled > 4.0 V, the oscillator is disabled and GATE will stay high. If the VFB pin is pulled < 0.49 V, GATE will stay low. Current Sense Pin. This pin is connected to the current sense resistor on the primary side. If VFB is floating, the GATE will go low if ISENSE = 195 mV (335 mV). If ISENSE > 275 mV (525 mV), Soft Start will be initiated. Gate Drive Output Pin. Capable of driving a 3.0 nF load. GATE is nominally clamped to 13.5 V. Ground Pin. FUNCTION
- 3
3 2
SYNC UVLO
4
4
SS
5
5
VFB
6
6
ISENSE
7 8
7 8
GATE GND
http://onsemi.com
5
CS5124, CS5126
SYNC (CS5126 ONLY) VCC UVLO COMP VCC
OSC DIS RAMP R F1 V5REF
- VREFOK +
+
F3 Q G1 S R Q
DRIVER GATE
VCC
+
+ -
G2
VREF = 5.0 V S
V 7.7 V/7.275 V
ENABLE
RESET DOMAIN
85 mV/s 170 mV/s G7 G3 V5REF
LINE UVLO COMP
-
V V5REF 10 A
4500
- +
+
TSHUT 150C/125C + V
+
2.62 V/2.45 V
VFB COMP PWM COMP
-
+
(1/5) V 490 mV 1/10
UVLO
+ -
/
V
VFB 1000 ISENSE
+
BIAS
(CS5124 ONLY)
+
REMOTE (SLEEP) COMP V 1.91 V/1.83 V
+
(125 mV) 60 mV (525 mV) 275 mV
+
SOFT START LATCH
F2 G5 VCC 2.9 R LINE AMP
- + -
2ND ICOMP
-
V
S R
Q (2.65 V) 2.90 V
BLANKING BLANK
G6
SET DOMAIN
V5REF
+ +
GND SS AMP
+ -
R
SS COMP
+
+
V
275 mV V V
2.0 V
1.32 V
+
SS
V
Figure 2. Block Diagram
THEORY OF OPERATION
Powering the IC
VCC can be powered directly from a regulated supply and requires 500 A of start-up current. The CS5124/6 includes a line bias pin (BIAS) that can be used to control a series pass transistor for operation over a wide input voltage. The BIAS pin will control the gate voltage of an N-channel MOSFET placed between VIN and VCC to regulate VCC at 8.0 V.
VCC and UVLO Pins
The UVLO pin has three different modes; low power shutdown, Line UVLO, and normal operation. To illustrate how the UVLO pin works; assume that VIN, as shown in the application schematic, is ramped up starting at 0 V with the UVLO pin open. The SS and ISENSE pins also start at 0 V. While the UVLO is below 1.8 V, the IC will remain in a low current sleep mode and the BIAS pin of the CS5124 is internally clamped to a maximum of 15 V. When the voltage
on the UVLO pin rises to between 1.8 V and 2.6 V the reference for the VCC UVLO is enabled and VCC is regulated to 8.0 V by the BIAS pin (CS5124 only), but the IC remains in a UVLO state and the output driver does not switch. When the UVLO pin exceeds 2.6 V and the VCC pin exceeds 7.7 V, the GATE pin is released from a low state and can begin switching based on the comparison of the ISENSE and VFB pins. The Soft Start capacitor begins charging from 0 V at 10 A. As the capacitor charges, a buffered version of the capacitor voltage appears on the VFB pin and the VFB voltage begins to rise. As VFB rises the duty cycle increases until the supply comes into regulation.
Soft Start
Soft Start is accomplished by clamping the VFB pin 1.32 V below the SS pin during normal start up and during restart after a fault condition. When the CS5124/6 starts, the Soft
http://onsemi.com
6
CS5124, CS5126
Start capacitor is charged from a 10 A source from 0 V to 4.9 V. The VFB pin follows the Soft Start pin offset by -1.32 V until the supply comes into regulation or until the Soft Start error amp is clamped at 2.9 V (2.65 V for the CS5126). During fault conditions the Soft Start capacitor is discharged at 10 mA.
Fault Conditions Second Threshold Comparator
The CS5124/6 recognizes the following faults: UVLO off, Thermal Shutdown, VREF(OK), and Second Current Threshold. Once a fault is recognized, fault latch F2 is set and the IC immediately shuts down the output driver and discharges the Soft Start capacitor. Soft Start will begin only after all faults have been removed and the Soft Start capacitor has been discharged to less than 0.275 V. Each fault will be explained in the following sections.
Under Voltage Lockout (UVLO)
Since the maximum dynamic range of the ISENSE signal in normal operation is 195 mV (335 mV for the CS5126), any voltage exceeding this threshold on the ISENSE pin is considered a fault and the PWM cycle is terminated. The 2nd ICOMP compares the ISENSE signal with a 275 mV (525 mV for the CS5126) threshold. If the ISENSE voltage exceeds the second threshold, F2 is set, the driver turns off, and the Soft Start capacitor discharges. After the Soft Start capacitor has discharged to less than 0.275 V Soft Start will begin. If the fault condition has been removed the supply will operate normally. If the fault remains the supply will operate in hiccup mode until the fault condition is removed.
VFB Comparator
The UVLO pin is tied to typically the midpoint of a resistive divider between VIN and GROUND. During a start up sequence, this pin must be above 2.6 V in order for the IC to begin normal operation. If the IC is running and this pin is pulled below 1.8 V, F2 shuts down the output driver and discharges the Soft Start capacitor in order to insure proper start-up. If the UVLO pin is pulled high again before the Soft Start capacitor discharges, the IC will complete the Soft Start discharge and, if no other faults are present, will immediately restart the power supply. If the UVLO pin stays low, then it will enter either the low current sleep mode or the UVLO state depending on the level of the UVLO pin.
Thermal Shutdown
The VFB comparator detects when the output voltage is too high. When the regulated output voltage is too high, the feedback loop will drive VFB low. If VFB is less than 0.49 V the output of the VFB comparator will go high and shut the output driver off.
Oscillator
The internally trimmed, 400 kHz (CS5124) or 200 kHz (CS5126) provides the slope compensation ramp as well as the pulse for enabling the output driver.
PWM Comparator and Slope Compensation
If the IC junction temperature exceeds approximately 150C the thermal shutdown circuit sets F2, which shuts down the output driver and discharges the Soft Start capacitor. If no other faults are present the IC will initiate Soft Start when the IC junction temperature has been reduced by 25C.
VREF(OK)
VREF(OK) is an internal monitor that insures the internal regulator is running before any switching occurs. This function does not trip the fault comparator like the other fault functions. To insure that Soft Start will occur at low line conditions the UVLO divider should be set up so that the VCC UVLO comparator turns on before the LINE UVLO comparator.
The CS5124/6 provides a fixed internal slope compensation ramp that is subtracted from the feedback signal. The PWM comparator compares peak primary current to a portion of the difference of the feedback voltage and slope compensation ramp. The 170 mV/s (85 mV/s for the CS5126) slope compensation ramp is subtracted from the voltage feedback signal internally. The difference signal is then divided by ten (five for the CS5126) before the PWM comparator to provide high noise rejection with a low voltage across the current sense network. (The effective ramp is 21 mV/s for the CS5124, and 18 mV/s for the CS5126). A 60 mV (125 mV for the CS5126) nominal offset on the positive input to the PWM comparator allows for operation with the ISENSE pin at, or even slightly below GND. A 4.3 k pull-up resistor internally connected to a 5.0 V nominal reference provides the bias current to for an optocoupler connection to the VFB pin.
http://onsemi.com
7
CS5124, CS5126
APPLICATION INFORMATION
UVLO and Thermal Shutdown Interaction
0.82
Maximum Duty Cycle
The UVLO pin and thermal shutdown circuit share the same internal comparator. During high temperature operation (TJ > 100C) the UVLO pin will interact with the thermal shutdown circuit. This interaction increases the turn-on threshold (and hysteresis) of the UVLO circuit. If the UVLO pin shuts down the IC during high temperature operation, higher hysteresis (see hysteresis specification) might be required to enable the IC.
BIAS Pin (CS5124 Only)
125C 25C -40C
0.77
The bias pin can be used to control VCC as shown in the main application diagram in Figure 1. In order to provide adequate phase margin for the bias control loop, the pole created by the series pass transistor and the VCC bypass capacitor should be kept above 10 kHz. The frequency of this pole can be calculated by Formula (1).
Pole Frequency + Transconductance of pass Transistor 2 p CV(CC)
(1)
0.72 200 kHz
300 kHz
400 kHz Frequency
500 kHz
600 kHz
Figure 4. CS5126 Maximum Duty Cycle vs. Frequency (Synchronized Operation)
The Line BIAS pin shows a significant change in the regulated VCC voltage when sinking large currents. This will show up as poor line regulation with a low value pull-up resistor. Typical regulated VCC vs BIAS pin sink current is shown in Figure 3.
8.3
If the converter is initially free running and a sync signal is applied, the current oscillator cycle will terminate and the oscillator will lock on to the sync signal. The SYNC pin works with a positive edge triggered signal. When the sync signal transitions high the current PWM cycle terminates and a new cycle begins as shown in Figure 5. The typical phase lag between the rising edge of the SYNC signal and the rising edge of the Gate is shown in Figure 6. When this pin is held high or low the internal clock determines the oscillator frequency.
SYNC
8.2
OSC
VCC
8.1
GATE
Figure 5. Synchronized Operation
8.0 140 130 Phase Lag 7.9 5.0 10 20 50 100 200 120 110 100 90 80
Bias Current (IBIAS)
Figure 3. Regulated VCC vs. BIAS Sink Current
The BIAS pin and associated components form a high impedance node. Care should be taken during PCB layout to avoid connections that could couple noise into this node.
Clock Synchronization Pin (CS5126 Only)
The CS5126 can be synchronized to signals ranging from 30% slower to several times faster than the internal oscillator frequency. If the part is synchronized to a fast signal, maximum duty cycle will be reduced as the frequency increases as shown in Figure 4.
70 200 kHZ
300 kHZ
400 kHZ
500 kHZ
600 kHZ
Figure 6. Typical Phase Lag between SYNC and GATE on
http://onsemi.com
8
CS5124, CS5126
Gate Drive
Rail to rail gate driver operation can be obtained (up to 13.5 V) over a range of MOSFET input capacitance if the gate resistor value is kept low. Figure 5 shows the high gate drive level vs. the series gate resistance with VCC = 8.0 V driving an IRF220.
8.5 8.0 Peak Voltage
When the output current is high enough for the ISENSE pin to exceed the first threshold, the PWM cycle terminates early and the converter begins to function more like a current source. The current sense network must be chosen so that the peak current during normal operation does not exceed the first current sense threshold.
Second Current Sense Threshold
7.5
7.0 6.5
6.0 0 0.3 0.5 2.5 Gate Resistor Value 5.0 11
Figure 7. Gate Drive vs. Gate Resistor Driving an IRF220 (VCC = 8.0 V)
A large negative dv/dt on the power MOSFET drain will couple current into the gate driver through the gate to drain capacitance. If this current is kept within absolute maximum ratings for the GATE pin it will not damage the IC. However if a high negative dv/dt coincides with the start of a PWM duty cycle, there will be small variations in oscillator frequency due to current in the controller substrate. If required, this can be avoided by choosing the transformer ratio and reset circuit so that a high dv/dt does not coincide with the start of a PWM cycle, or by clamping the negative voltage on the GATE pin with a schottky diode
First Current Sense Threshold
The second threshold is intended to protect the converter from over-heating by switching to a low duty cycle mode when there are abnormally high fast rise currents in the converter. If the second current sense threshold is tripped, the converter will shut off and restart in Soft Start mode until the high current condition is removed. The dead time after a second threshold over-current condition will primarily be determined by the time required to charge the Soft Start cap from 0.275 V nominal to 1.32 V. The second threshold will only be reached when a high dv/dt is present at the current sense pin. The signal must be fast enough to reach the second threshold before the first threshold turns off the driver. This will normally happen if the forward inductor saturates or when there is a shorted load. Excessive filtering of the current sense signal, a low value current sense resistor, or even an inductor that does not saturate during heavy output currents can prevent the second threshold from being reached. In this case the first current sense threshold will trip during each cycle of high output current conditions. The first threshold will limit output current but some components, especially the output rectifier, can overheat due to higher than normal average output current.
Slope Compensation
During normal operation the peak primary current is controlled by the level of the VFB pin (as determined by the control loop) and the current sense network. Once the signal on the ISENSE pin exceeds the level determined by VFB pin the PWM cycle terminates. During high output currents the VFB pin will rise until it reaches the VFB clamp. The first current sense threshold determines the maximum signal allowed on the ISENSE pin before the PWM cycle is terminated. Under this condition the maximum peak current is determined by the VFB Clamp, the slope compensation ramp, the PWM comparator offset voltage and the PWM on time. The nominal first current threshold varies with on time and can be calculated from Formulas (2) & (3) below.
CS5124 1st Threshold + CS5126 1st Threshold + 2.9 V * 170 mV ms 10 2.65 V * 85 mV ms 5.0 TON * 60 mV (2)
Current mode converters operating at duty cycles in excess of 50% require an artificial ramp to be added to the current waveform or subtracted from the feedback waveform. For the current loop to be stable the artificial ramp must be equivalent to at least 50% of the inductor current down slope and is typically chosen between 75% to 100% of the inductor down current down slope. To choose an inductor value such that the internal slope compensation ramp will be equal to a certain fraction of the inductor down current slope use the Formula (4).
1 Internal Ramp RSENSE (VOUT ) VRECTIFIER) NSECONDARY NPRIMARY (4)
Slope Value Factor + Inductor Value(H)
Calculating the nominal inductor value for an artificial ramp equivalent to 100% of the current inductor down slope at CS5126 nominal conditions, a 5.0 V output, a 200 m current sense resistor and a 4:1 transformer ratio yields
1 20 mV ms (5.0 V ) 0.3 V) 1 4 0.2 W 1.0 + 13.2 mH (5)
TON * 125 mV
(3)
http://onsemi.com
9
CS5124, CS5126
To check that the slope compensation ramp will be greater than 50% of the inductor down under all conditions, substitute the minimum internal slope compensation value and use 0.5 for the slope compensation value. Then check that the actual inductor value will always be greater than the inductor value calculated. During synchronized operation of the CS5126 the slope compensation ramp is reduced by 33%. If the CS5126 will be used in synchronized operation, the inductor value should be recalculated to work with the slope compensation ramp reduced to 67% of the normal value.
Powering the CS5124/6 from a Transformer Winding
There are numerous ways to power the CS5124/6 from a transformer winding to enable the converter to be operated at high efficiency over a wide input range. Two ways are shown in the application circuits. The CS5124 application circuit in Figure 1 is a flyback converter that uses a second flyback winding to power VCC. R4 improves VCC regulation with load changes by snubbing the turn off spike. Once the turn off spike has subsided the voltage of this winding is voltage proportional to the voltage on the main flyback winding. This voltage is regulated because the main winding is clamped by the regulated output voltage.
In the CS5126 application circuit in Figure 8 an extra winding is added to the forward inductor to power VCC. This winding is phased to conduct during the off time of the forward converter and performs the same function as the flyback winding above. A flyback winding from a forward transformer can also be used to power VCC. Ideally the transformer volt-second product of a forward converter would be constant over the range of line voltages and load currents; and the transformer inductance could be chosen to store the required level of energy during each cycle to power VCC. Even though the flyback energy is not directly regulated it would remain constant. Unfortunately in a real converter there are many non-ideal effects that degrade regulation. Transformer inductance varies, converter frequency varies, energy stored in primary leakage inductance varies with output current, stray transformer capacitances and various parasitics all effect the level of energy available for VCC. If too little energy is provided to VCC, the bootstrapping circuit must provide power and efficiency will be reduced. If too much energy is provided VCC rises and may damage the controller. If this approach is taken the circuit must be carefully designed and component values must be controlled for good regulation.
36-75VIN
L1 10 H C1 1.5 F 100 V R1 39 k D2 C2 1.5 F 100 V R6 17.4 k D3 11 V C5 1.0 F 25 V
CTX15-14526
T1 CTX15-14527 5VOUT
R2 200 k
Q1 F2T493
T2 Q2 IRF634 C6 390 pF R4 0.2 1/4W MBRB2060CT
C3 0.2 F 100 V
MMBD6100L
C12 0.01 F
R7 2.0 k
R3 30.1 k C7 47 F C8 47 F
ENABLE R9 SYNC 10 k C4 1000 pF R10 10 k C11 0.1 F
VCC GND UVLO GATE IS SYNC SS VFB CS5126 C10 1000 pF
C9 U2 0.01 F
TPS5908
R8 10 k ISOLATED RTN
48VRTN
Figure 8. Additional Application Diagram, 48 V to 5.0 V, 5.0 A Forward Converter using the CS5126
http://onsemi.com
10
CS5124, CS5126
PACKAGE DIMENSIONS
SO-8 D SUFFIX CASE 751-07 ISSUE V
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-8 45 165 Unit C/W C/W
http://onsemi.com
11
CS5124, CS5126
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
http://onsemi.com
12
CS5124/D

▲Up To Search▲

Price & Availability of CS5124

	To Download CS5124 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .